BUS ARBITRATION -
• The device that is allowed to initiate data transfers on bus at any given time is called bus-master.
• There can be only one bus master at any given time.
• Bus arbitration is the process by which next device to become the bus-master is selected and bus-mastership is transferred to it.
• There are 2 approaches to bus arbitration:
1) In centralized arbitration, a single bus-arbiter performs the required arbitration.
2) In distributed arbitration, all device participate in selection of next bus-master.
CENTRALIZED ARBITRATION -
• A single bus-arbiter performs the required arbitration (Figure: 4.20 & 4.21).
• Normally, processor is the bus. master unless it grants bus mastership to one of the DMA controllers.
• A DMA controller indicates that it needs to become busmaster by activating Bus-Request line(BR).
• The signal on the BR line is the logical OR of bus-requests from all devices connected to it.
• When BR is activated, processor activates Bus-Grant signal(BG1) indicating to DMA controllers that they may use bus when it becomes free. (This signal is connected to all DMA controllers using a daisy-chain arrangement). • If DMA controller-1 is requesting the bus, it blocks propagation of grant-signal to other devices. Otherwise, it passes the grant downstream by asserting BG2.
• Current bus-master indicates to all devices that it is using bus by activating Bus-Busy line (BBSY).
• Arbiter circuit ensures that only one request is granted at any given time according to a predefined priority scheme
A conflict may arise if both the processor and a DMA controller try to use the bus at the same time to access the main memory. To resolve these conflicts, a special circuit called the bus arbiter is provided to coordinate the activities of all devices requesting memory transfers.
DISTRIBUTED ARBITRATION -
• All device participate in the selection of next bus-master (Figure 4.22)
• Each device on bus is assigned a 4-bit identification number (ID).
• When 1 or more devices request bus, they → assert Start-Arbitration signal & → place their 4-bit ID numbers on four open-collector lines ARB 0 through ARB 3 .
• A winner is selected as a result of interaction among signals transmitted over these lines by all contenders.
• Net outcome is that the code on 4 lines represents request that has the highest ID number.
• Main advantage: This approach offers higher reliability since operation of bus is not dependent on any single device.
INTERRUPTS -
• I/O device initiates the action instead of the processor. This is done by sending a special hardware signal to the processor called as interrupt(INTR), on the interrupt-request line.
• The processor can be performing its own task without the need to continuously check the I/O device.
• When device gets ready, it will "alert" the processor by sending an interrupt-signal (Figure 4.5).
• The routine executed in response to an interrupt-request is called ISR(Interrupt Service Routine).
• Once the interrupt-request signal comes from the device, the processor has to inform the device that its request has been recognized and will be serviced soon. This is indicated by a special control signal on the bus called interrupt-acknowledge(INTA).
For example, pressing a keyboard key or moving a mouse plugged into a PS/2 port triggers hardware interrupts that cause the processor to read the keystroke or mouse position. Hardware interrupts can arrive asynchronously with respect to the processor clock, and at any time during instruction execution.
The addressing mode is the method to specify the operand of an instruction. The job of a microprocessor is to execute a set of instructions stored in memory to perform a specific task. Operations require the following:
For example, if we wanted to add the numbers 1 and 2 and get a result, mathematically we would likely write this as 1 + 2. In this case, our operator is (+), or the addition, and our operands are the numbers 1 and 2.
In a microprocessor, the machine needs to be told how to get the operands to perform the operation. The effective address is a term that describes the address of an operand that is stored in memory. There are several methods to designate the effective address of those operands or get them directly from the register. These methods are known as addressing modes.
With immediate addressing mode, the actual data to be used as the operand is included in the instruction itself. Let's say we want to store operand 1 into a register and then add operand 2. With immediate addressing mode, the data values 1 and 2 would be part of the instruction itself as shown below.
When using direct addressing mode, the address of the operand is specified in the instruction. The processor will retrieve the data directly from the address specified in the instruction. In this figure, the example shows how the instruction tells the processor where to get the data from in memory. The variable addr_of_2 is a pointer to the effective address of the operand.
There are no calculations required to retrieve the operand since the effective address (the address of the operand) is addressed directly. Like immediate addressing mode, the operand is limited to the size of 1 word (8 or 16 bits).
Register addressing mode indicates the operand data is stored in the register itself, so the instruction contains the address of the register. The data would be retrieved from the register.
BUS STRUCTURE -
• A bus is a group of lines that serves as a connecting path for several devices.
• Bus must have lines for data transfer, address & control purposes.
• Because the bus can be used for only one transfer at a time, only 2 units can actively use the bus at any given time.
• Bus control lines are used to arbitrate multiple requests for use of the bus.
• Main advantage of single bus: Low cost and flexibility for attaching peripheral devices.
• Systems that contain multiple buses achieve more concurrency in operations by allowing 2 or more transfers to be carried out at the same time. Advantage: better performance. Disadvantage: increased cost.
• The devices connected to a bus vary widely in their speed of operation. To synchronize their operational speed, the approach is to include buffer registers with the devices to hold the information during transfers. Buffer registers prevent a high-speed processor from being locked to a slow I/O device during a sequence of data transfers.
BASIC OPERATIONAL CONCEPTS -
• The processor contains ALU, control-circuitry and many registers.
• The instruction-register(IR) holds the instruction that is currently being executed.
• The instruction is then passed to the control-unit, which generates the timing-signals that determine when a given action is to take place
• The PC(Program Counter) contains the memory-address of the next-instruction to be fetched & executed.
• During the execution of an instruction, the contents of PC are updated to point to next instruction.
• The processor also contains „n‟ general-purpose registers R0 through Rn-1.
• The MAR (Memory Address Register) holds the address of the memory-location to be accessed.
• The MDR (Memory Data Register) contains the data to be written into or read out of the addressed location.
Following are the steps that take place to execute an instruction -
• The address of first instruction(to be executed) gets loaded into PC.
• The contents of PC(i.e. address) are transferred to the MAR & control-unit issues Read signal to memory.
• After certain amount of elapsed time, the first instruction is read out of memory and placed into MDR.
• Next, the contents of MDR are transferred to IR. At this point, the instruction can be decoded & executed.
• To fetch an operand, it's address is placed into MAR & control-unit issues Read signal. As a result, the operand is transferred from memory into MDR, and then it is transferred from MDR to ALU.
• Likewise required number of operands is fetched into processor.
• Finally, ALU performs the desired operation.
• If the result of this operation is to be stored in the memory, then the result is sent to the MDR.
• The address of the location where the result is to be stored is sent to the MAR and a Write cycle is initiated.
• At some point during execution, contents of PC are incremented to point to next instruction in the program. [The instruction is a combination of opcode and operand].
CRT stands for Cathode Ray Tube. CRT is a technology used in traditional computer monitors and televisions. The image on CRT display is created by firing electrons from the back of the tube of phosphorus located towards the front of the screen.
Once the electron heats the phosphorus, they light up, and they are projected on a screen. The color you view on the screen is produced by a blend of red, blue and green light.
Main Components of CRT are:-
1. Electron Gun: Electron gun consisting of a series of elements, primarily a heating filament (heater) and a cathode. The electron gun creates a source of electrons which are focused into a narrow beam directed at the face of the CRT.
2. Control Electrode: It is used to turn the electron beam on and off.
3. Focusing system: It is used to create a clear picture by focusing the electrons into a narrow beam.
4. Deflection Yoke: It is used to control the direction of the electron beam. It creates an electric or magnetic field which will bend the electron beam as it passes through the area. In a conventional CRT, the yoke is linked to a sweep or scan generator. The deflection yoke which is connected to the sweep generator creates a fluctuating electric or magnetic potential.
5. Phosphorus-coated screen: The inside front surface of every CRT is coated with phosphors. Phosphors glow when a high-energy electron beam hits them. Phosphorescence is the term used to characterize the light given off by a phosphor after it has been exposed to an electron beam.
DDA stands for Digital Differential Analyzer. It is an incremental method of scan conversion of line. In this method calculation is performed at each step but by using results of previous steps.
Step1: Start Algorithm
Step2: Declare x1,y1,x2,y2,dx,dy,x,y as integer variables.
Step3: Enter value of x1,y1,x2,y2.
Step4: Calculate dx = x2-x1
Step5: Calculate dy = y2-y1
Step6: If ABS (dx) > ABS (dy)
Then step = abs (dx)
Else
Step7: xinc=dx/step
yinc=dy/step
assign x = x1
assign y = y1
Step8: Set pixel (x, y)
Step9: x = x + xinc
y = y + yinc
Set pixels (Round (x), Round (y))
Step10: Repeat step 9 until x = x2
Step11: End Algorithm
Computer graphics deals with generating images with the aid of computers. Today, computer graphics is a core technology in digital photography, film, video games, cell phone and computer displays, and many specialized applications. A great deal of specialized hardware and software has been developed, with the displays of most devices being driven by computer graphics hardware. It is a vast and recently developed area of computer science.
Applications -
System Software -
Application Software -
RADIO BUTTONS -
Radio buttons are useful when you want the user to select a single item from a small list of choices and you want all the choices to be visible.
Radio buttons are added via the element.
The buttons are made mutually exclusive (i.e., only one can be chosen) by sharing the same name attribute.
The checked attribute is used to indicate the default choice, while the value attribute works in the same manner as with theelement.
CHECKBOXES Checkboxes are used for getting yes/no or on/off responses from the user.
Checkboxes are added via the element.
We can also group checkboxes together by having them share the same name attribute.
Each checked checkbox will have its value sent to the server.
Like with radio buttons, the checked attribute can be used to set the default value of a checkbox
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